Product Description
FPGA Prototyping Using Verilog Examples will provide you with a hands-on introduction to Verilog synthesis and FPGA programming through a “learn by doing” approach. By following the clear, easy-to-understand templates for code development and the numerous practical examples, you can quickly develop and simulate a sophisticated digital circuit, realize it on a prototyping device, and verify the operation of its physical implementation. This introductory text that will provide you with a solid foundation, instill confidence with rigorous examples for complex systems and prepare you for future development tasks. ... Read more

Customer Reviews (3)

Fun with Verilog and FPGAs!
I wholeheartedly recommend this book to any student that feels the need to brush up on their Verilog and FPGA skills. The projects are very exciting and interesting. The pong game example was simply AMAZING. During my college career most of my Verilog/FPGA courses were in the first half, the second half was more microcontroller/software engineering oriented. So it was a natural choice to brush up again on HDL fundamentals before going into job interviews. Initially I did a quick read through of the book to get a basic idea of the author's style and methodology. My second pass through the book I coded along and did some of the suggested examples. This book is worth the money and the time. The author is easy to follow and easy to understand. I'll also be purchasing the VHDL book from the same author.

Please be aware that this is not a book on the Verilog language. It's a project based guide to writing efficient and synthesizable code for FPGA implementation. This book is written to be used with the Xilinx Spartan-3 board, so it is vital you have this board or a version that is somewhat compatible.

TL;DR: The author is clear, and easy to understand. The examples are COOL! If you love project based learning then this is the book for you.

Excellent text with real examples
I have done logic on and off since my college days (some 20 years ago), but have spent most of my adult life in software.This book, one of three I purchased on the subject, did the best job of bringing me up to speed quickly on FPGA design and Verilog.It went into detail on the difficult to understand topics like the differences in blocking and non-blocking assignments and had great examples on all topics.The back part of the book has some more detailed applications such as UARTS and VGA signal production and these were less interesting to me since they were not related to my project, but in the end the book got me over the hump of being able to write HDL and know what it is going to do.

Best introductory book
This is perhaps the best introductory Verilog book.It introduces the digital system design methodology and demonstrates the key language concepts and constructs via a series of practical examples, all of them can be physically implemented and tested in an inexpensive Xilinx FPGA board.

There are three parts:
-Part 1 introduces key Verilog language constructs, and systematically shows how to construct combinational circuit, sequential circuit, FSM, and FSMD (FSM with data path) by these constructs.
-Part 2 utilizes the methodologies and techniques of part 1 to design interface and control circuits for an array of I/O modules of the prototyping board, including UART, keyboard, mouse, SRAM, graphic VGA, and textual VGA.
-Part 3 introduces PicoBlaze (an 8-bit soft-core micro-controller) and demonstrates how to integrate a processor to an FPGA design and develop customized I/O.

Pros:
-It utilizes a hands-on approach to introduce Verilog and design methodology.
-It introduces Verilog from hardware's point of view (rather than C's point of view) and emphasizes the key concepts behind HDL.
-The design methodology and coding practice used the in the book are sound and can be applied to larger system.
-It contains an advanced chapter that clarifies several confusing Verilog constructs, such as blocking/non-blocking assignments and signed data type.
-It contains a chapter on soft-core micro-controller and shows the integration of general-purpose processor and customized circuit.

Cons (actually caveats):
-The book is more towards applying Verilog for digital system design rather than the Verilog language. It only covers key Verilog language constructs.You may need another book to learn the complete "language."
-You need to purchase a prototyping board (around $100) to take full advantage of this book.
-The book covers PicoBlaze (a simple 8-bit processor), not its the full-blown big brother, MicroBlaze (a 32-bit processor). The later perhaps is too complicated for an introductory book.
... Read more

Product Description
This text presents basic implementation strategies forarithmetic datapath designs and methodologies utilized in the digitalsystem. The author implements various datapath designs for addition,subtraction, multiplication, and division. Theory is presented toillustrate and explain why certain designs are chosen. Eachimplementation is discussed in terms of design choices and howparticular theory is invoked in the hardware. Along with the theory that emphasizes the design in question, Verilogmodules are presented for understanding the basic ideas that accompanyeach design. Structural models are implemented to guarantee correctsynthesis and for incorporation into VLSI schematic-capture programs.From the modules, the reader can easily add or modify existing code tostudy current areas of research in the area of computer arithmetic.The emphasis is on the arithmetic algorithm and not the circuit. Forany design, both algorithmic and circuit trade-offs should be adheredto when a design is under consideration. Therefore, the idea is toimplement each design at the RTL level so that it may be possiblyimplemented in many different ways (i.e. standard-cell orcustom-cell). Thus, professionals, researchers, students, and thosegenerally interested in computer arithmetic can understand howarithmetic datapath elements are designed and implemented. Also included is a CD-ROM which contains the files discussed inthe book. The CD-ROM includes additional files utilized inpreparing the designs in Verilog including scripts to automaticallygenerate Verilog code for parallel carry-save and tree multipliers.Each Verilog design also contains each module including testbenches tofacilitate testing and verification. ... Read more

Customer Reviews (3)

Digital Computer Arithmetic Datapath Design Using Verilog HDL: CD-ROM included
I would have liked to review this book, but unfortunately Amazon twice sent me a defect book that did not have the CD.

Too many missing details
The content of this book is very disappointing. Too many details are missing. In many cases, the authors describe implementations without getting into the details of how they reached it. Because of these missing details, it is hard to understand the reasonning behind some of the trade-offs described in the book. It lacks clarity in several areas. Even with some experience in the area, I was left too many times trying to figure out what the authors meant.

Code is easy to understand
Book works well with other arithmetic books like Koren's.All the code is on a CD and its great to finally see an implementation that's easy to understand since its all written structurally. ... Read more

Product Description

The exponential increase in transistor density on computer chips, supporting Moore¿s law now for four decades, poses new design challenges to engineers and computer scientists alike. New techniques for managing complexity must be developed if circuits are to take full advantage of the vast numbers of transistors available.

This book investigates both the design of high-level languages for hardware description and techniques involved in translating these high-level languages to silicon. The author introduces the first-order functional language SAFL, designed specifically for behavioral hardware description, and describes the implementation of its associated silicon compiler. Finally, the SAFL language is extended with pi-calculus style channels and channel passing and primitives for structural-level circuit description. The semantics of these languages is formalized and results are presented arising from the generation of real hardware exploiting these techniques.

This monograph is based on the author¿s PhD work conducted at the Computer Laboratory of the University of Cambridge, UK, under the supervision of Dr. Alan Mycroft.

Product Description

Verification is increasingly complex, and SystemVerilog is one of the languages that the verification community is turning to. However, no language by itself can guarantee success without proper techniques. Object-oriented programming (OOP), with its focus on managing complexity, is ideally suited to this task.

With this handbook—the first to focus on applying OOP to SystemVerilog—we’ll show how to manage complexity by using layers of abstraction and base classes. By adapting these techniques, you will write more "reasonable" code, and build efficient and reusable verification components.

Both a learning tool and a reference, this handbook contains hundreds of real-world code snippets and three professional verification-system examples. You can copy and paste from these examples, which are all based on an open-source, vendor-neutral framework (with code freely available at www.trusster.com).

Learn about OOP techniques such as these:

• Creating classes—code interfaces, factory functions, reuse
• Connecting classes—pointers, inheritance, channels
• Using "correct by construction"—strong typing, base classes
• Packaging it up—singletons, static methods, packages

Product Description

Verification is too often approached in an ad hoc fashion. Visually inspecting simulation results is no longer feasible and the directed test-case methodology is reaching its limit. Moore's Law demands a productivity revolution in functional verification methodology.

Writing Testbenches Using SystemVerilog offers a clear blueprint of a verification process that aims for first-time success using the SystemVerilog language. From simulators to source management tools, from specification to functional coverage, from I's and O's to high-level abstractions, from interfaces to bus-functional models, from transactions to self-checking testbenches, from directed testcases to constrained random generators, from behavioral models to regression suites, this book covers it all.

Writing Testbenches Using SystemVerilog presents many of the functional verification features that were added to the Verilog language as part of SystemVerilog. Interfaces, virtual modports, classes, program blocks, clocking blocks and others SystemVerilog features are introduced within a coherent verification methodology and usage model.

Writing Testbenches Using SystemVerilog introduces the reader to all elements of a modern, scalable verification methodology. It is an introduction and prelude to the verification methodology detailed in the Verification Methodology Manual for SystemVerilog.  It is a SystemVerilog version of the author's bestselling book Writing Testbenches: Functional Verification of HDL Models.

Customer Reviews (1)

High-level, abstract approach and guidelines for the *experienced* Verification engineer
The book's title is a bit misleading.It does NOT teach you Systemverilog (for Verification) -- there is a separate book by Chris Spear ("Systemverilog for Verification") sold by the same publisher that focuses more on Systemverilog syntax and language features.This book is NOT a tutorial (i.e. beginner's guide) on how to write testbenches -- although it does go through the basic concepts, objectives, and challenges in writing maintainable/re-usable testbench environments, most of the textbook examples are too cryptic/advanced for an entry-level engineer.

So then, what does this book focus on?Well, the book focuses on general guidelines to writing re-usuable, high-level testbenches.The author uses Systemverilog as the language to communicate his concepts, but as I said before, the book does NOT teach you Systemverilog.(To the author's credit, he is very upfront about that in foreward/intro section.)

Who should read it:
Experienced verification engineers with a basic understanding of Systemverilog (and why it's superior to Verilog), who want some ideas/examples of how to deploy Systemverilog's advanced features (like classes, structs, random vars) in a verification environment.

What I liked:
The use of classes to encapsulate bus-functional-models (BFMs), how to create and manage variations of a basic BFM (using extended/derived classes), etc.He also shows how to combine randomization with classes, to create random stimulus-sequences.

What could have been improved:
I was hoping the book would cover SVA (systemverilog assertions) in greater depth, but I guess there are other books for that.He also superficially mentions "configurations" -- that is a feature in Verilog-2001 and VHDL-93.The book should have covered that in more depth (even though it's not a new Systemverilog feature), as it pertains to testcase management and organization.

What you should have:
You need a good background and experience in ASIC/RTL-verification -- this book is not an introduction to testbench concepts, or the Systemverilog language!You need to know some Systemverilog language, so either have a different book (like Chris Spear's "Systemverilog for Verification"), or the official IEEE Systemverilog 1800-2005 LRM next to your side.Though not necessary, it's helpful to have a basic understanding about object-oriented programming, because the examples in the book use Systemverilog's classes (and inheritance) to illustrate a lot of points.Object-oriented concepts would otherwise be foreign to most engineers working in the hardware field.

Ohter notes:
The book makes numerous references to the VMM (Verilog Methodology Manual), which is a separate book by the same author.VMM is probably as close to a 'canned' (i.e. pre-built) testbench environment as you can get.If you run Synopsys VCS in your company, then VMM is worth investigatation.Unfortunately, I've heard it doesn't run well on competing simulators (Cadence, Mentor), as Systemverilog support is still in its infancy. ... Read more

Product Description
The focus of Assertion-Based Design, Second Edition is three-fold:

-How to specify assertions,
-How to create and adopt a methodology that supports assertion-based design (predominately for RTL design),
-What to do with the assertions and methodology once you have them.

Customer Reviews (3)

Not really useful
The topics are discussed in a too generic way to let the reader take advantage of the book.

great book (though assertions are not everything ...)
Comprehensive and serious, it is worth reading.
Some comments (for the first edition):
-Assertions and white-box checkers are not exactly the same.
(sometimes white-box checkers are more natural in say `e' than is PSL or SVA that are mostly temporal based)

- Ooops , In all SVA examples"disable iff (rst_n)"... ;-)

- A small one,Page 204example 6-46:
" assert property (@posedge clk) disable iff(rst_n)
not (SMQueNew -> $isunknown(...)))"

The `not' should have been after the `->' , the current semantics is wrong.


The book also lacks mentioning of assertions inside dynamic TB objects.
(`e' supports it, maybe other languages too).


Though, my key comment is that there is a lot more toverification than assertions( e.g. Testbench implementation ).

Ran Keren

When assertion fires ...
Once again, after "Principles of Verifiable RTL Design" written with L. Bening, Harry Foster wrote the book that made new level of standards in ASIC community. Even with notice that, as a Verplex Systems guy, he evidently advertise specific Formal Verification techniques, this book could not get anything then 5 big stars. Not only that this is the only book on the market that cover important topics like Assertions, this is also well and systematically written book, full of examples in OVL, PSL and SystemVerilog. And whatever ASIC designers say that they don't have time for Assertions, future is going in this direction. Book is written equally for design and verification engineers, but also for system architects and everybody involved in ASIC development. This book probably will not shake ASIC design world as previous bestseller from the same author, but it presents state of the art in covered area from the man who knows his job very well ... ... Read more

Product Description
The Definitive, Up-to-Date Guide to Digital Design with SystemVerilog: Concepts, Techniques, and Code

To design state-of-the-art digital hardware, engineers first specify functionality in a high-level Hardware Description Language (HDL)—and today’s most powerful, useful HDL is SystemVerilog, now an IEEE standard. Digital System Design with SystemVerilog is the first comprehensive introduction to both SystemVerilog and the contemporary digital hardware design techniques used with it.

Building on the proven approach of his bestselling Digital System Design with VHDL, Mark Zwolinski covers everything engineers need to know to automate the entire design process with SystemVerilog—from modeling through functional simulation, synthesis, timing simulation, and verification. Zwolinski teaches through about a hundred and fifty practical examples, each with carefully detailed syntax and enough in-depth information to enable rapid hardware design and verification. All examples are available for download from the book's companion Web site, zwolinski.org.

Coverage includes

• Using electronic design automation tools with programmable logic and ASIC technologies
• Essential principles of Boolean algebra and combinational logic design, with discussions of timing and hazards
• Core modeling techniques: combinational building blocks, buffers, decoders, encoders, multiplexers, adders, and parity checkers
• Sequential building blocks: latches, flip- flops, registers, counters, memory, and sequential multipliers
• Designing finite state machines: from ASM chart to D flip-flops, next state, and output logic
• Modeling interfaces and packages with SystemVerilog
• Designing testbenches: architecture, constrained random test generation, and assertion-based verification
• Describing RTL and FPGA synthesis models
• Understanding and implementing Design-for-Test
• Exploring anomalous behavior in asynchronous sequential circuits
• Performing Verilog-AMS and mixed-signal modeling

Product Description

Integrating formal property verification (FPV) into an existing design process raises several interesting questions. This book develops the answers to these questions and fits them into a roadmap for formal property verification – a roadmap that shows how to glue FPV technology into the traditional validation flow. The book explores the key issues in this powerful technology through simple examples that mostly require no background on formal methods.